PURPOSE: To perform an optimum data transfer corresponding to the number of processor element(PE).

CONSTITUTION: In a parallel computer system composed of plural processor elements (PE) 1 and a network 2, the data width of the interface with the network 2 on the side of the processor element(PE) can be selected by the integral multiple of a prescribed unit data length (w), a data transfer cycle can be selected by the integral multiple of the basic clock (τ) of the parallel computer system. A data transfer is performed by defining a prescribed number (N) of the processor element(PE) 1 to be connected with the network 2 as a reference, selecting the data transfer width and the data transfer cycle by defining the unit data length (w) and the basic clock (τ) as units and connecting with the network 2.