Title:
DATA TRANSFER CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JP2002175261
Kind Code:
A
Abstract:
To provide a data transfer control circuit capable of specifying immediately UART or the like wherein interruption is generated.
Interruption signals INT0-INT7 of plural UARTs 16A, 16-1 to 16-7, in a PC card 10A are given to an interruption state register ISR installed instead of a general scratch register SCR of the UART 16A. The state of the interruption state register ISR is given to a PC (personal computer) 1 as an interruption signal INT through AND 17. Therefore, when interruption is generated in some UART and the interruption is executed into the PC 1 by the interruption signal INT, the PC 1 can specify immediately the UART wherein the interruption is generated, by reading out the interruption state register ISR of the UART 16A.
Inventors:
SHINAGAWA NORIAKI
MAEDA SHUSAKU
MAEDA SHUSAKU
Application Number:
JP2000370532A
Publication Date:
June 21, 2002
Filing Date:
December 05, 2000
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G06F13/14; G06F9/48; G06F13/12; G06F13/24; G06K19/07; (IPC1-7): G06F13/14; G06F13/12; G06F13/24; G06K19/07
Domestic Patent References:
| JPH04352057A | 1992-12-07 | |||
| JPS6158037A | 1986-03-25 |
Attorney, Agent or Firm:
Kakimoto Kyosei
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