Title:
DATA TRANSFER CONTROLLER AND ELECTRONIC EQUIPMENT
Document Type and Number:
Japanese Patent JP3543649
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a data transfer controller and electronic equipment capable of reducing the overheads of processings and transferring data at a high speed with the hardware of a small scale.
SOLUTION: In this data transfer controller of an IEEE1394 standard, between a link core and a CPU, a built-in RAM for storing packets capable of random access is provided other than a FIFO. The storage area of the RAM is separated into a header area, a data area and the work area of the CPU and the header area and the data area are separated into areas for reception and for transmission. By using TAG, the header of a reception packet is written in the header area and the data are written in the data area. The data area is separated into the areas for isochronous transfer and for asynchronous transfer. A pointer for variably controlling the size of the respective areas of the RAM is prepared and the size of the respective areas is dynamically and variably controlled even after supplying power. The respective areas are turned to a ring buffer structure. The size of the area for storing the header and data of one packet is fixed.
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Inventors:
Takao Ogawa
Takuya Ishida
Yoshiyuki Kamihara
Takuya Ishida
Yoshiyuki Kamihara
Application Number:
JP32154198A
Publication Date:
July 14, 2004
Filing Date:
October 27, 1998
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
H04L12/28; H04L12/40; (IPC1-7): H04L12/40
Domestic Patent References:
| JP10285223A | ||||
| JP10135985A | ||||
| JP2310649A | ||||
| JP59501435A |
Attorney, Agent or Firm:
Inoue Ichi
Yukio Fuse
Mitsue Obuchi
Yukio Fuse
Mitsue Obuchi