Title:
データ転送制御装置
Document Type and Number:
Japanese Patent JP5423483
Kind Code:
B2
Abstract:
In a data transfer control apparatus, a transfer start address and a transfer size are acquired from a peripheral circuit. A command is issued in response to an activation signal from the peripheral circuit. When data transfer is performed between the main memory unit and the peripheral circuit, completion of issuance of all of commands corresponding to the transfer start address and transfer size is detected. The transfer size is retained until the end of data transfer. A next command is issued prior to completion of data transfer for one command, and a next activation signal is received upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size. Next transfer start address and transfer size are acquired upon detection of completion of issuance of all of the commands corresponding to the one transfer start address and transfer size.
Inventors:
Atsushi Kawada
Application Number:
JP2010047388A
Publication Date:
February 19, 2014
Filing Date:
March 04, 2010
Export Citation:
Assignee:
株式会社リコー
International Classes:
G06F13/28
Domestic Patent References:
| JP2005157717A | ||||
| JP2006172107A | ||||
| JP2000148663A | ||||
| JP63186357A |
Attorney, Agent or Firm:
Hideo Takino