Title:
データ転送装置
Document Type and Number:
Japanese Patent JP3998532
Kind Code:
B2
Abstract:
The number of pulses of a clock signal CLK-A is circularly counted in a count range from "0" to "7", and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of "3" and "7", and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.
Inventors:
Katsuya Mizumoto
Hiroshi Shirota
Ryosuke Okuda
Yata Kazuaki
Hiroshi Shirota
Ryosuke Okuda
Yata Kazuaki
Application Number:
JP2002230423A
Publication Date:
October 31, 2007
Filing Date:
August 07, 2002
Export Citation:
Assignee:
Renesas Technology Corp.
Renesas Design Co., Ltd.
Renesas Design Co., Ltd.
International Classes:
G06F13/36; H04L7/00; G06F1/04; G06F1/12; G06F13/38; G06F13/42; H03K3/00; H03K19/0175; H03K19/094; H03M9/00; H04L7/02; H04L25/49
Domestic Patent References:
| JP2002135132A | ||||
| JP2002141808A | ||||
| JP2001268142A | ||||
| JP4257133A | ||||
| JP4154329A |
Attorney, Agent or Firm:
Hiroaki Sakai