PURPOSE: To attain synchronization with a clock inside a receiver without losing any clock cycle at a data transfer device synchronizing a transmitter/ receiver with the same clock.
CONSTITUTION: A variable delay circuit 1 delays received data and outputs them to a data non-fixed time detection part 118. Latches L0 and L2 respectively have latch timing at a gap before and after the latch timing of a latch L1 corresponding to variable delay circuits 503 and 504. At the time of control, the delay amount of both the variable delay circuits 503 and 504 is fixed at a sufficiently smaller value in comparison with a transfer cycle, the delay amount of the variable delay circuit 1 is increased, and a discrimination circuit 7 detects the front edge of received data. Next, the delay amount of both the variable delay circuits 503 and 504 is successively increased while mutually keeping them at the same value and the rear edge of received data is detected. At such a time, the latch timing of the latch L1 becomes the optimum point of a maximum margin. At the time of usual operating, the discrimination circuit 7 detects deviation from the optimum point, fine control is performed to the delay amount of the variable delay circuits 1, 503 and 504 and the latch timing of received data is maintained at the optimum point.
DOI TOSHIO
ISHIBASHI KENICHI
HAYASHI TAKEHISA
YAMAGIWA AKIRA
