PURPOSE: To make a titled device useful as an interface which is usable for other processors, by providing a memory storing data at each address of a peripheral device, a memory controlling circuit and a transmitter between the control circuit and the peripheral device.

CONSTITUTION: Data from an input device 12 are added with addresses and supplied to a memory controlling circuit 16 via a peripheral control circuit 19 and transmitters 18, 17 and written in a memory 15. The controlling circuit 16 detects the transfer state of the content of memory at each prescribed time. The data in the memory 15 is transmitted to a bus 11 with access of a processor. The output data from the processor are written in the memory 15, the controlling circuit 16 detects the area after a prescribed time and transmits the information together with the address of a device 13 while no accessing is done. Since the content of the memory 15 can be made coincident with the data of an input and output device after a prescribed time, an IF of the processor and that of the input and output device can be manufactured independently.