PURPOSE: To shorten the common bus occupancy time and also to improve the bus use efficiency by combining plural input/output controllers and plural channels, and executing a data transfer at low speed and high speed.

CONSTITUTION: A CPU10 is provided with a main memory device 8, an arithmetic unit 7 and a bus 9, uses a bus coupling device 6 and a channel device 14 as each channel, and executes a data transfer between a display controller 4 and a magnetic disk controller 11 through a common bus 1. The device 11 transfers a data read out of a disk device 3, to the device 8 through a device 14. The device 11 has an address peculiar to the bus 1, receives the data as the slave of the bus 1 by an access from the bus 1, and at the time of a data transfer to the device 8, the data is unified or divided in the device 14. As a result, the use efficiency of the bus 9 can be raised and also the bus 9 and can be used separately, and the bus occupancy time is shortened.