PURPOSE: To reduce the hardware for a multiplexer and a data bus, by converting an output data of each memory plane into a data train of 1-bit, selecting a serial data, performing serial parallel conversion again and transmitting the result to a control section of each device.

CONSTITUTION: A parallel data in 32-bit from 0W31 of a memory plane 30 is entried to a shift register 31, shifted left and outputted as a serial output data in 1-bit from 0-bit to 31-bit every time a clock pulse is inputted, and inputted to a multiplexer 33. A serial data selected at it is arranged in time division from 0 bit to the 31-th bit and inputted to a shift register 35. This serial data 34 is replaced with 32 sets of clock pulses from 0-bit to the 31-th bit, serial/parallel conversion is made, a parallel data 36 in 32-bit is again outputted, and this output is transmitted to a device control section. Thus, the circuit constitution of the multiplexer is simplified.