PURPOSE: To make it possible to transfer data in a rectangular area and a sequential area by one starting by introducing left and right high speed collective shifters of data transfer width and function that disenables memory writing in unit of bit.

CONSTITUTION: One word is read from a source address SAD and shifted to the right by a shifter. A destination memory indicated by a bit mask register FMSK is disenabled, and destination write data DDB is written in a destination address DAD. When the destination address is DAD+2, a bit designated by a bit mask register BMSK is disenabled, and writing of bit is prohibited. When transfer of one horizontal line is completed, segment horizontal width SPH is added to the source address register SADR, and segment width DPH is added to a destination address register DADR, and the address is positioned to next line.