To efficiently suppress noise and power consumption of RAM, and to improve reliability.
If the number of bits, in which the data of 64-bit width mutually change at the same time, exceeds a predetermined threshold value, the data is outputted by inverting polarity of each bit, but in other case, it is outputted with no polarity inverted. An error correction code of 7-bit width is applied to the data that has been outputted and to an inversion instruction signal representing whether or not the number of bits that has changed has exceeded the threshold value. The outputted data, the inversion instruction signal, and the error correction code are transmitted. By using the error correction code that has been transmitted, error code correction is applied to the data and the inversion instruction signal. If the number of bits in which the inversion instruction signal that has been applied with the error code correction has changed represents that it has exceeded the threshold value, the data that has been applied with the error code correction is outputted by inverting polarity of each bit, but in other case, the data that has been applied with error code correction is outputted.
| JP4423519 | Decoding method of error correction code |
| WO/2015/191184 | JOINT DEMODULATING AND DEMAPPING OF DIGITAL SIGNAL |
| JPS63124641 | DATA COMMUNICATION TERMINAL EQUIPMENT |
| JP2009021981A | 2009-01-29 | |||
| JP2006179131A | 2006-07-06 |
| US0009011A | 1852-06-15 |
Ishibashi Masayuki
Masaaki Ogata