Title:
DC FEEDBACK CIRCUIT
Document Type and Number:
Japanese Patent JP3462408
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To obtain a DC feedback circuit that stably suppresses a DC offset even when a base band filter is present in a feedback loop that is operated for a non-signal period.
SOLUTION: A sample-and-hold circuit 7 detects a DC component appearing at an output terminal 6 by a mixer 2 and an base band filter 5 for a non-signal period and stores the DC component in a hold capacitor C, and keeps the DC component stored in the capacitor C for periods other than the non-signal period. A comparator 9 compares the DC component with a reference voltage Vref, outputs a signal in response to the result to a level shift circuit 4 inserted in a base band signal path, which shifts a level of the DC component to suppress the output DC offset based on the outputted signal. Through the control above, for the non-signal period, the DC feedback loop is operated to make the feedback loop stable by changing a frequency characteristic of the filter so as to suppress the DC offset at the signal output terminal 6, and the control signal given to the DC level shift circuit 4 is maintained for periods other than the non-signal period thereby attaining suppression of the DC offset for all the periods.
Inventors:
Toshiharu Kawaguchi
Application Number:
JP33475598A
Publication Date:
November 05, 2003
Filing Date:
November 25, 1998
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
H03D7/00; H04B1/26; (IPC1-7): H04B1/26; H03D7/00
Domestic Patent References:
| JP730596A | ||||
| JP9284160A | ||||
| JP11252186A |
Attorney, Agent or Firm:
Saichi Suyama
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