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Patent Searching and Data


Title:
DEBUG DEVICE
Document Type and Number:
Japanese Patent JPS6346549
Kind Code:
A
Abstract:

PURPOSE: To simplify the circuit constitution together with its easy operation by storing en bloc the using section information on a memory space of a program to be debugged into a memory circuit and giving an access to this memory circuit to read out the using section information.

CONSTITUTION: When the using section information is set to all addresses, the programs in a memory 220 and a substitution memory 32 are executed by an emulation CPU 310. In this case, an operator switches an address switching circuit 342 by an address switch signal so that the circuit 342 selects the address given from a CPU 310 and gives it to a using section information memory circuit 340. As a result, an address if outputted from the CPU 310 via an address bus (a) is always applied to the circuit 340 via the circuit 342. The circuit 340 consists of a RAM and therefore the data on a single byte stored in a given address, that is, the using section information is read out of the circuit 340.


Inventors:
YOSHIKAWA HIROSHI
Application Number:
JP19047286A
Publication Date:
February 27, 1988
Filing Date:
August 15, 1986
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F11/28; (IPC1-7): G06F11/28
Attorney, Agent or Firm:
Kazuo Sato