Title:
DECIDING SYSTEM FOR MEMORY PARITY ERROR
Document Type and Number:
Japanese Patent JPH01263854
Kind Code:
A
Abstract:
PURPOSE: To improve the working efficiency in a debugging mode by using a deciding part to decide whether a parity error is produced in a using area or an unused area.
CONSTITUTION: A parity check part 2 detects the parity errors with collation of the parity bits obtained in the write and read states of a memory 1. A deciding part 3 is connected to an address bus 4 and decides whether a parity error is produced in a using area or an unused area based on the read address information on an address bus 4 at reception of a parity error detecting signal from the part 2. Based on the result of said decision, the part 3 outputs a hardware error signal or a program error signal to the outside.
More Like This:
| JP3227628 | INFORMATION PROCESSING SYSTEM |
| JPS5469349 | ERROR CORRECTING SYSTEM |
| JP3604101 | FLASH MEMORY CONTROLLER |
Inventors:
KUMAKURA HIROSHI
Application Number:
JP9300588A
Publication Date:
October 20, 1989
Filing Date:
April 15, 1988
Export Citation:
Assignee:
NEC CORP
International Classes:
G06F12/16; (IPC1-7): G06F12/16
Domestic Patent References:
| JPS5638636A | 1981-04-13 | |||
| JPS59208660A | 1984-11-27 | |||
| JPS6158054A | 1986-03-25 |
Attorney, Agent or Firm:
Naoki Kyomoto (3 outside)