PURPOSE: To provide a compact decimal adder which serves as the core of a decimal computing unit in an addition table system for each decimal digit.

CONSTITUTION: A decimal adder consists of an even number adding circuit 1 which divides each digit of input into an even number component shown in higher 3 bits and an odd number component shown in a single lower bit, adds together even number components as an input, and outputs the lower 3 digit bits of the sum as the even number components and a single carry bit added to a higher order digit as a carry odd component respectively, a 3-input binary addition circuit 2 which outputs higher order bit of the sum as an even number component and a lower order bit of the sum as an odd number component respectively, and an even number-plus-2 addition circuit 3 which adds the even number component received from the circuit 1 or another circuit 3 to the higher order bit of the sum of the circuit 2 and outputs lower 3 digit bits of the sum as the even number components and a single carry bit added to a higher order digit as a carry odd number component respectively. In such a constitution, the circuits 1 are combined in a tournament form for each digit and both circuits 2 and 3 are cascaded together.