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Patent Searching and Data


Title:
DECODER FOR BURST ERROR CORRECTION CODE
Document Type and Number:
Japanese Patent JPH03104320
Kind Code:
A
Abstract:

PURPOSE: To minimize the delay required for decoding without segmenting a code by providing a means detecting all zeros of low-order bits of a syndrome register, a means controlling an output of the syndrome register and a means adding outputs of a data register and the syndrome register.

CONSTITUTION: After the input of a received word is finished to a data register 2 and a syndrome register 4, when all 0s of the low-order bits of the syndrome register 4 are detected by an all 0 detector 8, it means that a burst error of a prescribed length or below exists in the high-order bits of the syndrome register 4, and the contents of the syndrome register 4 and the data register 2 are added to apply error correction.


Inventors:
OMURA HIDEO
Application Number:
JP24290189A
Publication Date:
May 01, 1991
Filing Date:
September 18, 1989
Export Citation:
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Assignee:
NEC CORP
International Classes:
H03M13/00; (IPC1-7): H03M13/00
Attorney, Agent or Firm:
Uchihara Shin