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Title:
DECODER CIRCUIT
Document Type and Number:
Japanese Patent JPS5916426
Kind Code:
A
Abstract:

PURPOSE: To obtain a decoder signal without producing an unnecessary pulse, by using a T type flip-flop constituting a synchronizing counter through inversion.

CONSTITUTION: An output of the T type flip-flops TF1, TF2 is inverted with inverters G20, G21, G22 and G23 to form the outputs of -Q1', Q', -Q2', Q2', and a decoded output is obtained by using them, where OUT1=Q'.Q2' and OUT2= -Q1'.-Q2' are obtained. No unnecessary pulse is given in the decoded outputs OUT1 and OUT2, because signals inverted at inverters G20∼G23 is decoded and a signal to be going to "H" goes to "H" after a signal to be going to "L" goes to "L" among the signals Q', -Q1', Q2', -Q2'.


Inventors:
HIKINO MIKIO
Application Number:
JP12740082A
Publication Date:
January 27, 1984
Filing Date:
July 19, 1982
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03K19/091; H03K21/08; H03M7/00; (IPC1-7): H03K21/08
Domestic Patent References:
JPS54120541A1979-09-19
JPS5381058A1978-07-18
Attorney, Agent or Firm:
Masuo Oiwa