PURPOSE: To suppress the latch-up phenomenon of a CMOS circuit, by providing a means whose turning-on and turning-off are controlled by supplementary address signals of real and supplementary address signals and which selects one out of plural driving means.

CONSTITUTION: Address signals are divided into real and supplementary address signals and turning-on and turning-off of a selecting means SWi are controlled by one of the supplementary address signal A2 as it is or a signal which is obtained by pre-decoding one of the real address signals A3WA7 so as to select either one of 1st and 2nd driving means I1 and I2 which respectively drive 1st and 2nd word line driving circuits WD1 and WD2. Therefore, a decoder circuit whose output signal is set at a 32μm pitch is provided and the distance between a P channel area and N channel area can be made longer because the arranging pitch is expanded. Thus the latch-up resisting quantity of a CMOS circuit can be improved.