Title:
DECODER FOR CODED MODULATION SIGNAL
Document Type and Number:
Japanese Patent JP3422088
Kind Code:
B2
Abstract:
PURPOSE: To reduce the circuit scale by providing an extract section used to extract signal point discrimination information specifying a signal point of each group closest to data at a received point to the decoder so as to reduce the number of low-order bits added to soft discrimination decoding for the signal point of the group of the received data to the utmost.
CONSTITUTION: An extract section 1 provided newly in parallel with a reception input of a decoder 10 for a coded modulation signal extracts required output data X, Y from received data x, y and converts them. Then a non-coding bit discrimination section 30 specifies a signal point resident in a region closest to the received data x, y among, e.g. 4 wide regions A to D represented by a high-order bit even when low-order bits of the received data x, y indicate any value. Since the extract section l does not take much time to extract the output data X, Y from the received data x, y, the delay time to be provided to the inputs X, Y by a delay section 20 required for the non-coding bit discrimination section 30 to specify one signal point among the regions based on the inputs X, Y is enough to be small.
Inventors:
Shigeyuki Yoshioka
Takeshi Inoue
Tadashi Nakamura
Takeshi Inoue
Tadashi Nakamura
Application Number:
JP22328294A
Publication Date:
June 30, 2003
Filing Date:
September 19, 1994
Export Citation:
Assignee:
富士通株式会社
International Classes:
H04L27/00; H04L1/00; H04L27/38; (IPC1-7): H04L27/38; H04L1/00; H04L27/00
Domestic Patent References:
| JP330524A | ||||
| JP7131493A |
Attorney, Agent or Firm:
Junichi Yokoyama
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