PURPOSE: To highly integrate a decoder by commonly using two of three N- channel type transistors connected in series at a ground side for both NAND dates.

CONSTITUTION: Three P-channel type MOS transistors P11, P12, P13 and two P-channel type MOS transistors P14, P15 are connected in parallel, and address data A1, A2 and B1 are input to the gates of the transistors P11, P12, P13 and P14, P15. Three N-channel type MOS transistors N11, N12, N13 are connected to a ground side. 2-input NAND gates are formed of the transistors N12, N13 and the transistors P14, P15, and 3-input NAND gates are formed of the transistors P11, P12, P13 and the transistors N11, N12, N13.