To realize operation at a high-speed clock frequency when achieving entropy decoding processing by hardware.
A decoding device performing the entropy decoding of a bit stream to be inputted for outputting has shifters 102, 105 that are provided in parallel to the input of the bit stream and successively shift the inputted bit stream for holding. A header analyzer 106 is connected to the shifter 105 and decodes coded data corresponding to a header in data supplied by the shifter 105. Additionally, a decoder 103 decodes coded data corresponding to symbol data in data supplied by the shifter 102 for outputting. Each of the decoder 103 and the header analyzer 106 outputs an amount of shift 1 and an amount of shift 2 according to the progress of processing, and an OR circuit 104 calculates the logical OR of them to generate a shift signal for supplying to the shifters 102, 105.
Shiro Takayanagi
Yasuhiro Otsuka
Shuji Kimura
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