To eliminate the need of an oscillator in a decoder by using one bit for specifying whole pulse width, calculating measuring time from whole pulse width and immediately measuring the signal level of a digital signal when measurement time after start elapses with respect to other succeeding bits.
The digital signal 50 is the sequence of eight bits 51 and a first bit 49 and a start bit are not decoded. The time periods of all the bits are the same and they have whole pulse widths 54. One bit is started by a steep ascending part 100 and it ascends to a high signal level 52. It is held for 2/3 of whole pulse width without a change in the first bit. Then, it steeply descends to a low signal level 53 and it does not change for remaining pulse width. A second bit becomes the high signal level 52 again by the steep ascending part 100 and it does not change for 1/3 of whole pulse width. Then, it becomes the low signal level 53 by steep descending and it does not change for 2/3 of whole pulse width.
| WO/2017/091689 | MESHED ARCHITECTURE RACKMOUNT STORAGE ASSEMBLY |
| JP2015046715 | COMMUNICATION CIRCUIT AND INFORMATION PROCESSING DEVICE |
BAUER JOACHIM
OTT GUENTHER
KOEHLER DIETMAR
