Title:
欠陥分析器
Document Type and Number:
Japanese Patent JP5107506
Kind Code:
B2
Abstract:
The present invention provides methods, devices, and systems for analyzing defects in an object such as a semiconductor wafer. In one embodiment, it provides a method of characterizing defects in semiconductor wafers during fabrication in a semiconductor fabrication facility. This method comprises the following actions. The semiconductor wafers are inspected to locate defects. Locations corresponding to the located defects are then stored in a defect file. A dual charged-particle beam system is automatically navigated to the vicinity defect location using information from the defect file. The defect is automatically identified and a charged particle beam image of the defect is then obtained. The charged particle beam image is then analyzed to characterize the defect. A recipe is then determined for further analysis of the defect. The recipe is then automatically executed to cut a portion of the defect using a charged particle beam. The position of the cut is based upon the analysis of the charged particle beam image. Ultimately, a surface exposed by the charged particle beam cut is imaged to obtain additional information about the defect.
Inventors:
Teshima Janet
Party Daniel E
Hudson James Y
Party Daniel E
Hudson James Y
Application Number:
JP2004552102A
Publication Date:
December 26, 2012
Filing Date:
November 12, 2003
Export Citation:
Assignee:
F-I-I Company
International Classes:
H01L21/66; G01B15/00; G01N21/956; G01N23/225; H01L21/00; G01N21/00
Domestic Patent References:
| JP200290312A | ||||
| JP3266718B2 | ||||
| JP2000268768A | ||||
| JP11265679A |
Attorney, Agent or Firm:
Yamaguchi International Patent Office
Kunio Yamaguchi
Kunio Yamaguchi