Title:
耐欠陥性及び耐故障性回路相互接続
Document Type and Number:
Japanese Patent JP2007505436
Kind Code:
A
Abstract:
Methods for increasing defect tolerance and fault tolerance in systems containing interconnected components, in which a signal level is classified as belonging to one of a plurality of different, distinguishable classes based on one or more thresholds separating the signal-level classes, and defect-and-fault tolerant systems embodying the methods. An electronic-device embodiment including an array of nanowire crossbars, the nanoscale memory elements within the nanowire crossbars addressed through conventional microelectronic address lines, and a method embodiment for providing fault-tolerant interconnection interfaces with electrically distinguishable signal levels are described. In the described embodiment, in order to interconnect microelectronic address lines with the nanowire crossbars within the electronic memory, an address encoding technique is employed to generate a number of redundant, parity-check address lines to supplement a minimally required set of address signal lines needed to access the nanoscale memory elements.
Inventors:
Quakes, Philip, Jay
Williams, Earl, Stanley
Serrossi, Gadir
Williams, Earl, Stanley
Serrossi, Gadir
Application Number:
JP2006526265A
Publication Date:
March 08, 2007
Filing Date:
September 08, 2004
Export Citation:
Assignee:
Hewlett-Packard Development Company
International Classes:
G11C29/42; G06F11/10; G11C8/10; G11C8/20; G11C13/00; G11C17/00; G11C17/06
Domestic Patent References:
| JP2003187589A | 2003-07-04 | |||
| JP2003031693A | 2003-01-31 |
Foreign References:
| US6256767B1 | 2001-07-03 |
Attorney, Agent or Firm:
Satoshi Furuya
Takahiko Mizobe
Kiyoharu Nishiyama
Takahiko Mizobe
Kiyoharu Nishiyama