Title:
DEFLECTION CIRCUIT
Document Type and Number:
Japanese Patent JP3947594
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To correct orthogonal error and a parallelogram error in raster generation.
SOLUTION: A raster correction circuit 200 is coupled with a horizontal deflection circuit 100 in order to properly move scanning lines for a upper half and a lower half of a raster shaped to be a parallelogram to generate a rectangular raster as a whole. The raster correction circuit 200 is coupled with a horizontal deflection coil LH via a raster centering circuit network including an inductance coil LC and a capacitor CC. The inductance coil LC has a higher inductance than that of the horizontal deflection coil LH and then a lower peak to peak current is flowed to the coil. A sawtooth wave voltage with a vertical frequency drives respectively transistors(TRs) Q2, Q3, resulting that a raster correction current with the vertical frequency flows to the raster correction circuit 200.
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Inventors:
Walter Truscaro
Peter Ronald Knight
Laurence edward smith
Peter Ronald Knight
Laurence edward smith
Application Number:
JP8242997A
Publication Date:
July 25, 2007
Filing Date:
March 17, 1997
Export Citation:
Assignee:
THOMSON CONSUMER ELECTRONICS,INCORPORATED
International Classes:
H04N3/16; G09G1/04; H04N3/233; (IPC1-7): H04N3/16; G09G1/04
Domestic Patent References:
| JP58039170A | ||||
| JP4005768U | ||||
| JP57166461U |
Attorney, Agent or Firm:
Riki Kikoshi
Kozo Aoyama
Kozo Aoyama
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