Title:
DELAY CIRCUIT FOR ANALOG SIGNAL
Document Type and Number:
Japanese Patent JP3391249
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a delay circuit in which low frequency noise disturbance can be removed.
SOLUTION: At the time of writing, an input analog signal Vin is stored in odd number memory cell M1, M3,..., Mn-1 and an inverted input analog signal Vin is stored in even number memory cell M2, M4,..., Mn. At the time of reading, a signal read out from even number memory cell M2, M4,..., Mn is inverted and combined, by a switch SH0, with a signal read out from odd number memory cell M1, M3, ..., Mn-1 to produce an output analog signal Vout. When a low frequency noise is mixed in the delay circuit, a voltage value stored in a capacitor C1-Cn is varied but since it is read out while repeating forward and reverse rotation, noise component can be shifted to a separable high region frequency.
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Inventors:
Akihiko Toda
Masao Noro
Toshio Maeshima
Masao Noro
Toshio Maeshima
Application Number:
JP5972798A
Publication Date:
March 31, 2003
Filing Date:
March 11, 1998
Export Citation:
Assignee:
Yamaha Corporation
International Classes:
G11C27/02; H03H11/26; H03H19/00; (IPC1-7): G11C27/02; H03H11/26; H03H19/00
Domestic Patent References:
| JP6152331A | ||||
| JP5342897A | ||||
| JP5290595A |
Attorney, Agent or Firm:
Kawasakizaki Kenji (1 person outside)
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