Title:
DELAY CIRCUIT FOR POWER SUPPLY
Document Type and Number:
Japanese Patent JP3353771
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a power supply delay circuit that can control rise times of multiple output voltages and reduces an EMI(electromagnetic interference) noise, and the delay time of which is accurate.
SOLUTION: The circuit has two regulators (1 and 2) including transistor converting and outputting an input voltage (5 V) to the specified voltages (2.5 V and 3.5 V). Each regulator has at least more than two input terminals. In the regulator 1, the input voltage (5 V) is charged, to an input terminal, the output voltage (2.5 V) from the regulator 2 is charged to other input terminal 61.
Inventors:
Tenshu Shigeno
Application Number:
JP2000019608A
Publication Date:
December 03, 2002
Filing Date:
January 28, 2000
Export Citation:
Assignee:
NEC
International Classes:
G05F1/00; G05F1/10; (IPC1-7): G05F1/00; G05F1/10
Domestic Patent References:
| JP146114A | ||||
| JP158294U | ||||
| JP464989U |
Attorney, Agent or Firm:
Opening Muneaki