PURPOSE: To attain excellent delay accuracy, to ensure the reliability regardless of the temperature and to attain the high speed small-sized delay circuit by storing valid signal only at sampling to a capacitance in a form of a charge.
CONSTITUTION: Plural delay circuits 10 connected in series as plural stages are used and switches SW1, SW2 are opened/closed reverse to each other synchronously with a sampling period. Assuming that a charging voltage of a capacitor C1 when no amplifier A1 is employed is aV and the capacitor C1 is charged up to a voltage cV by the amplifier A1, then the gain is set to c/a. When the capacitor C1 is charged up to the voltage aV, the switch SW1 is opened, the switch SW2 is closed, the potential of a capacitor C2 is multiplied by c/a with an amplifier A2 and the capacitor C1 is charged up to the potential aV in a prescribed time. After the capacitor C1 reaches the voltage aV in one cycle as above-mentioned, the potential is extracted at the outside of the delay circuit 10 by a buffer B1 and a sample value deviated by the sampling period is obtained.
MUTO HIROSHI
SUGAWARA TAKAO
KASAI KIICHIROU
MIZOSHITA YOSHIBUMI
