PURPOSE: To avoid the increase in an input terminal for selecting a delay element by using a counter output for a selective signal to select a desired delay element by the selective circuit.

CONSTITUTION: A counter circuit 6 is brought into the initial state, that is, the state in which a delay element 3a is selected by inputting a reset signal to a reset terminal 7b. The output of the counter as a selective signal is counted up sequentially by inputting a clock signal to a control signal input terminal 7a. The counter output is inputted to a selective circuit 4 as the selective signal. For example, when the delay time of a delay element 3b is desired to be obtained, the clock is once inputted after resetting. The selection of the required delay element is implemented by two external input terminals, that is, the control signal input terminal 7a and the reset terminal 7b. Thus, increase in the number of input terminals for the delay element selection is avoided.