PURPOSE: To reduce circuit scale by extracting a status(ST) bit while selecting either ST extraction according to a delayed/ST extracting clock, delayed/frame signal and delayed/data or ST extraction according to an ST extracting clock not to be delayed, frame signal and data, corresponding to a delay loading/ unloading signal.

CONSTITUTION: A selector 10 selects either of respective two signals according to a delay loading/unloading control signal (g) while receiving a control signal extracting clock (a), delayed control signal extracting clock (b) delaying this control signal extracting clock only for prescribed time, frame signal (c), delayed frame signal (d) delaying this frame signal only for prescribed time, data (e) and delayed data (f) delaying this data only for prescribed time. A control signal extracting circuit 11 outputs a control signal and a data in the prescribed bit of the frame while receiving the clock, frame signal and data outputted from the selector 10. Thus, the several dozens of bit shift registers for delaying the ST bit are not required and the circuit scale is reduced.