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Title:
DELAY DISPATCH CONTROLLER
Document Type and Number:
Japanese Patent JPH05324354
Kind Code:
A
Abstract:

PURPOSE: To easily control dipatch delay by holding information concerning a context immediately before control is shifted to an interruption processing or to an OS processing inside a program status work (PSW).

CONSTITUTION: A shift source information saving part 321 saves data where a bit at a position being the same as the position of a non-task flag inside PSW is '1' as shift source information in a stack and, after that, a non-task flag setting part 33 permits the present non-task flag inside PSW to be '1'. When control is shifted from an OS mainbody processing shifting part 322 to the OS mainbody processing 323 so that the processing is completed, a shift source context judging part 324 judges that the context of a shift source is a non-task through the use of previously saved shift source information and returns to the interruption processing of a calling sauce. Then, in the returned interruption processing, an interruption source context judging part 314 judges that l the shift source is the task and shifts control to a stack recovering part 34 so that control is shifted to a schedule start judging part 35.


Inventors:
IWAMURA YOSHIYUKI
Application Number:
JP12436692A
Publication Date:
December 07, 1993
Filing Date:
May 18, 1992
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
G06F9/46; G06F9/48; (IPC1-7): G06F9/46; G06F9/46
Attorney, Agent or Firm:
Akira Kobiji (2 outside)



 
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