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Title:
DELAY LOCK LOOP
Document Type and Number:
Japanese Patent JPH0453325
Kind Code:
A
Abstract:

PURPOSE: To obtain optimum acquisition of synchronization locking and synchronization tracking characteristic by setting a pulling-in enable range wider than that of one delay lock loop at the time of pulling-in and providing the same characteristics as that of one delay lock loop in the tracking state.

CONSTITUTION: A switch 5 selects either a spread code A or B to act a delay lock loop as one delay lock loop or 2- delay lock loop. The spread code A is used to act the delay lock loop as 2- delay lock loop to widen the locking rage wider than a conventional 1- delay lock loop at the time of pulling-in just after an acquisition pulse is inputted. On the other hand, the spread code B is used to act the delay lock loop as 1- delay lock loop in the synchronization tracking state and to obtain the same synchronization tracking characteristic as that of the conventional 1- delay lock loop. Thus, the optimum acquisition of synchronization and synchronization tracking characteristic are obtained.


Inventors:
KATAOKA NOBUHISA
Application Number:
JP16353890A
Publication Date:
February 20, 1992
Filing Date:
June 21, 1990
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H04J13/00; H04B1/7085; (IPC1-7): H04J13/00
Attorney, Agent or Firm:
Hiroaki Tazawa (1 person outside)



 
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