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Patent Searching and Data


Title:
DELAY SIMULATION DEVICE
Document Type and Number:
Japanese Patent JPH0773223
Kind Code:
A
Abstract:

PURPOSE: To enable the execution of a sufficiently exact delay simulation by completely expressing the wiring delay value that wired has.

CONSTITUTION: An extraction means 1 reads connection description data from a design data file 4 and extracts wired information based on the connection description data. A model generation means 2 generates wired element models having output elements by the number of branching destination based on the branching destination described in the extracted wired information. A delay value table preparation means 3 prepares a wiring delay value table 5 holding the wiring delay values of the routes from the input terminal of the wired element model to the output terminal based on the information from the model generation means 2 and sets the wiring delay value calculated based on the wiring delay value or the connection description data defined by the connection description data to the wiring delay value table 5.


Inventors:
KAWACHI TOSHIHIKO
Application Number:
JP17117593A
Publication Date:
March 17, 1995
Filing Date:
June 16, 1993
Export Citation:
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Assignee:
NEC CORP
International Classes:
G06F11/25; G06F17/50; (IPC1-7): G06F17/50; G06F11/25
Domestic Patent References:
JPH03184175A1991-08-12
JPS6395579A1988-04-26
JPS63257875A1988-10-25
JPH04205661A1992-07-27
JPH03189872A1991-08-19
Attorney, Agent or Firm:
Yanagi Kawa Shin