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Patent Searching and Data


Title:
DELAY TIME DETECTION CIRCUIT IN MULTI-DIRECTION MULTIPLEX COMMUNICATION EQUIPMENT
Document Type and Number:
Japanese Patent JPS6125339
Kind Code:
A
Abstract:

PURPOSE: To attain ease of initial phase matching at a slave station by providing an N-adic ring counter, a pulse expander and a pattern comparator possible for setting an initial value so as to attain tracking in the range where an initial adjustment burst signal does not give effect on the other operating burst.

CONSTITUTION: A demodulator 100 of a delay time detection circuit of a multi- direction multiplex device demodulates an initial adjustment burst 1 transmitted from a slave station and the N-adic ring counter 101 possible for setting an initial value outputs the n-th pulse 5 by using a reference timing signal 4 according to the state output 11 of the N-adic ring counter 106. The pulse expander 102 transmits a pulse 6 of a prescribed with (M-bit) by using the pulse 5. The pulse 6 is fed to a shift register 103, which reads an output of the demodulator 2 by using the clock 3 by the width of the pulse 6. A demodulation pattern 7 from the register 103 and a reference pattern 8 are compared by a pattern comparator 104 and the result 9 of comparison controls the counter 106 via a gate circuit 105.


Inventors:
NIINA SABURO
Application Number:
JP14592984A
Publication Date:
February 04, 1986
Filing Date:
July 16, 1984
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04J3/00; H04J3/06; (IPC1-7): H04J3/00
Attorney, Agent or Firm:
Uchihara Shin (1 person outside)