PURPOSE: To output an output timing signal which has been delayed to a delay time with high accuracy by constituting the respective delaying circuit bodies of delaying circuits so that a delay time given to a timing signal is selected suitably in advance.

CONSTITUTION: In a delaying circuit U1, for instance, a delaying circuit body D2 is selected by a selecting circuit S, based on the contents of control information W1, and in a delaying circuit U2, for instance, a delaying circuit body D1 is selected by the selecting circuit S, based on the contents of control information W2, and also, in a delaying circuit U3, for instance, a delaying circuit body D3 is selected by the selecting circuit S, based on the contents of control information W3. In this way, an output timing signal Q2 which has been delayed against an input timing signal Q1 by a delay time TR can be outputted as an output timing signal which has been delayed against the input timing signal Q1 by a delay time being the nearest to a set value TP.