To reduce memory capacity by making a memory shared for a butterfly operation and a delay memory for FFT window calculation.
An OFDM demodulator 1 uses an input buffer memory 21 in an FFT arithmetic circuit 8 and delays a signal outputted from a fc correction circuit 7, in the case of calculating an FFT window for the first OFDM symbol. The demodulator 1 also uses the delay memory 31, having a capacity for a guard interval and delays a guard interval part in the case of calculating an FFT window for OFDM symbols subsequent to the first OFDM symbol. The demodulator 1 calculates the signal correlation between the guard interval and its copy source from the delayed signal, and calculates an FFT window on the basis of a part having high correlation.
OKADA TAKAHIRO
MIYATO YOSHIKAZU
OZAKI YASUNARI
Next Patent: DEVICE FOR SEPARATING SIGNAL COMPONENT, FILTER DEVICE, RECEIVER, COMMUNICATIONS EQUIPMENT AND COMMUN...