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Title:
FM/PLL DEMODULATOR
Document Type and Number:
Japanese Patent JPS6024705
Kind Code:
A
Abstract:

PURPOSE: To obtain good FM receiving function by controlling a voltage controlling oscillator of a signal system PLL circuit by other PLL circuit.

CONSTITUTION: An AND circuit 9 makes outputs of loop filters 6, 13 as an input, obtains the logical product and inputs its output to a VCO5. The circuit 9, together with a phase comparator 4, the VCO5 and a filter 6, constitutes the first PLL circuit 10 to which a output from an intermediate frequency amplifier 3 is inputted. An error signal from the loop filter 6 of the first PLL circuit 10 and an error signal from the loop filter 13 of the second PLL circuit 14 are inputted to the AND circuit 9, and oscillating frequency of the VCO5 is controlled by an output signal from the AND circuit 9.


Inventors:
KAWABATA HIDEO
Application Number:
JP13391283A
Publication Date:
February 07, 1985
Filing Date:
July 20, 1983
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP
International Classes:
H03D3/02; H03D3/24; (IPC1-7): H03D3/02
Attorney, Agent or Firm:
Mamoru Takada (1 person outside)



 
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