Title:
デマルチプレクサ回路、及び半導体集積回路
Document Type and Number:
Japanese Patent JP7116342
Kind Code:
B2
Abstract:
To provide a demultiplexer circuit that can secure a timing margin in a case of performing data conversion.SOLUTION: A demultiplexer circuit includes: a first demultiplexer that converts a first input signal with a first bit width into a first intermediate signal with a second bit width larger than the first bit width on the basis of a first conversion clock signal that demultiplies a first clock signal; a second demultiplexer that converts a second input signal with the first bit width into a second intermediate signal with the second bit width on the basis of a second conversion clock signal that demultiplies a second clock signal having the same frequency as the first clock signal and having a first phase difference; and third and fourth demultiplexers that respectively convert the first and second intermediate signals into first and second output signals with a third bit width larger than the second bit width on the basis of a third conversion clock signal that demultiplies the first conversion clock signal.SELECTED DRAWING: Figure 5
Inventors:
Tatsuya Sakae
Hideki Kano
Hideki Kano
Application Number:
JP2021001305A
Publication Date:
August 10, 2022
Filing Date:
January 07, 2021
Export Citation:
Assignee:
Socionext Inc.
International Classes:
H04L7/033; H03K5/00; H03K5/15; H03K17/00; H03K21/00
Domestic Patent References:
| JP2017060050A | ||||
| JP2010183452A | ||||
| JP2013251916A | ||||
| JP2010035186A |
Foreign References:
| US20130107987 | ||||
| KR1020060051084A | ||||
| WO2010097846A1 |
Attorney, Agent or Firm:
Kokubun Takaetsu
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