Title:
【発明の名称】集積回路チップ上のイメージ除去ミキサー回路
Document Type and Number:
Japanese Patent JP2994458
Kind Code:
B2
Abstract:
An IF mixer circuit in a receiver implemented in integrated circuits employs a pair of doubly balance mixers, one injected with a local oscillator reference signal in phase while the quadrature phase of the reference signal is injected into the second mixer. A phase shift circuit adds another 90 DEG phase shift to the output of the second mixer, and the in-phase and out-of-phase signals are applied to a summing circuit to attenuate unwanted mixer products and reinforce the desired IF signal. The balanced elements of the 90 DEG phase shift circuit employ a transistor with equal emitter and collector resistances, a diode-connected transistor in series with the collector load resistance, and a collector-to-base capacitor, which provide a constant-amplitude phase shift in a unity gain structure independent of current, to produce a precise 90 DEG phase shift. Emitter current is adjustable to compensate for production variation in the absolute value of the fixed resistance, i.e., by varying the current in the transistor and diode, the dynamic resistance offsets the fixed resistance variation.
Inventors:
Asari Don H
Battice Karl Earl
Battice Karl Earl
Application Number:
JP51113690A
Publication Date:
December 27, 1999
Filing Date:
July 30, 1990
Export Citation:
Assignee:
Hattori Seiko Co., Ltd.
Seiko Epson Corporation
Seiko Epson Corporation
International Classes:
H04B1/10; H03D7/16; H03D7/18; H04B1/12; (IPC1-7): H04B1/10; H03D7/18
Domestic Patent References:
| JP5272514A |
Attorney, Agent or Firm:
Minoru Nakamura (6 outside)