Title:
【発明の名称】雑音消去方法及び雑音消去装置
Document Type and Number:
Japanese Patent JP2882364
Kind Code:
B2
Abstract:
In accordance with the present invention, for noise cancellation, a reference noise signal is input to signal-to-noise (SN) power ratio estimating circuitry via a reference signal input terminal. The SN power ratio estimating circuitry causes its adaptive filter for producing a pseudonoise signal from the reference noise signal to operate. The circuitry detects error signal power and pseudonoise signal power out of the pseudonoise signal and other signals, and then outputs an estimate of an SN power ratio based on the detected power. A first delay circuit is connected to the output terminal of the above circuitry. A comparator compares an estimate of an input to and an estimate of an output from the first delay circuit, and produces greater one of the two estimates as an expanded estimate. A step size output circuit controls, based on the expanded estimate, the step size of a second adaptive filter connected to the reference signal input terminal via a second delay circuit. A subtracter subtracts a pseudonoise signal output from the second adaptive filter from a received signal sequentially delayed by a third and a fourth delay circuit, thereby cancelling a background noise signal component contained in the received signal.
More Like This:
Inventors:
IKEDA SHIGEJI
Application Number:
JP15381696A
Publication Date:
April 12, 1999
Filing Date:
June 14, 1996
Export Citation:
Assignee:
NIPPON DENKI KK
International Classes:
G10L15/20; G10L21/0208; G10L21/0224; G10L21/0264; H03H17/00; H03H17/08; H03H21/00; H04M1/00; (IPC1-7): G10L9/00; G10L3/02; H03H17/00; H03H17/08; H03H21/00; H04M1/00
Domestic Patent References:
| JP918291A | ||||
| JP654394A | ||||
| JP7225595A | ||||
| JP6186997A | ||||
| JP667693A | ||||
| JP715787A |
Attorney, Agent or Firm:
Matsuura