Title:
【発明の名称】シミュレーション方法および装置
Document Type and Number:
Japanese Patent JP2715993
Kind Code:
B2
Abstract:
At least two test instructions are sequentially simulated. Concurrently the number of clocks taken for simulating at least two test instructions are counted. The peripheral processing program relating to at least two test instructions are simulated for the number of clocks counted after simulating at least two test instructions.
Inventors:
Shinobu Aoki
Application Number:
JP13948095A
Publication Date:
February 18, 1998
Filing Date:
June 06, 1995
Export Citation:
Assignee:
NEC
International Classes:
G06F11/28; G06F9/455; G06F11/36; (IPC1-7): G06F9/455
Domestic Patent References:
| JP6324883A | ||||
| JP6250874A | ||||
| JP6208480A | ||||
| JP6202903A | ||||
| JP695919A | ||||
| JP2118849A | ||||
| JP25140A |
Attorney, Agent or Firm:
Naotaka Ide