Title:
【発明の名称】半導体集積回路メモリのためのテスト信号発生器およびテスト方法
Document Type and Number:
Japanese Patent JP2779538
Kind Code:
B2
Abstract:
A test signal generator for a semiconductor integrated circuit memory, wherein when transfer transistors (20, 21, 14, 15) are rendered conductive, a test data cloumn is supplied from an I/O line pair (11, 12) to a column of a register (10) and stored therein. When a transfer (67) is rendered conductive, the test data column written in the register is written in a column of a memory cell (22) in the same pattern and when transfer transistors (16, 17) are rendered conductive, the test data column written in the register is inverted and the, written in the memory cell column, Data in the memory cell column is read out by a word line (13) and amplified by a sense amplifier (5), so that the data and the test data stored in the register are compared by a coincidence detection circuit 8 to detect whether it is coincident or not.
Inventors:
ARIMOTO KAZUTAMI
MATSUDA YOSHIO
OOISHI TSUKASA
TSUKIDE MASAKI
FUJISHIMA KAZUYASU
MATSUDA YOSHIO
OOISHI TSUKASA
TSUKIDE MASAKI
FUJISHIMA KAZUYASU
Application Number:
JP5400290A
Publication Date:
July 23, 1998
Filing Date:
March 05, 1990
Export Citation:
Assignee:
MITSUBISHI DENKI KK
International Classes:
G11C11/401; G11C11/409; G11C29/00; G11C29/10; G11C29/12; G11C29/34; G11C29/56; (IPC1-7): G11C29/00; G11C11/401
Domestic Patent References:
| JP61292298A | ||||
| JP61145799A | ||||
| JP63106990A | ||||
| JP57105891A | ||||
| JP53145431A | ||||
| JP5383538A | ||||
| JP5914838B2 |
Attorney, Agent or Firm:
Fukami Hisaro (3 outside)