Title:
【発明の名称】プログラマブル論理マトリクスを試験するための回路構成及び方法
Document Type and Number:
Japanese Patent JP2726395
Kind Code:
B2
Abstract:
A circuit architecture (1) for testing a programmable logic matrix (2), e.g. the PLA type, comprises a series (7) of input latches (ILi) and a corresponding series (8) of output latches (OLi) connected to the matrix (2) and test information paths structured with at least one data bus (11) and one address bus (12). The input latch (7) and output latch (8) are connected electrically to the test data bus (11) and the test address bus (12) and this allows matrix testing with considerable time saving compared with the known art.
Inventors:
MACCARRONE MARCO (IT)
OLIVO MARCO (IT)
OLIVO MARCO (IT)
Application Number:
JP29700494A
Publication Date:
March 11, 1998
Filing Date:
November 30, 1994
Export Citation:
Assignee:
ST MICROELECTRONICS SRL (IT)
International Classes:
G01R31/28; G01R31/3185; G06F7/00; G06F11/22; G11C29/48; (IPC1-7): G06F11/22; G01R31/28; G06F7/00
Domestic Patent References:
| JP5553453A | ||||
| JP60169949A | ||||
| JP6280738A | ||||
| JP6037905B2 |
Attorney, Agent or Firm:
Soga Doteru (6 people outside)