PURPOSE: To increase the signal transmitting speed of gate wiring so as to shorten gate array testing time by reducing the resistance of the gate wiring connecting gate electrodes of a transistor for testing gate arrays to each other and increasing the thickness of an insulating film on which the gate wiring is laid so as to reduce the capacitance of the gate wiring.

CONSTITUTION: The title transistors 21 are arranged on a gate array 10 at prescribed intervals and their source-drain areas 23 are connected to, for example, the source-drain areas 15 of transistors 12 constituting the gate array 10 and an interlayer insulating film is formed on the gate array 10. In addition, gate wiring 47 which has a resistance smaller than that of the gate electrode 22 of each transistor 21 and is connected to each gate electrode is also formed on the interlayer insulating film.