Title:
DESIGNING METHOD OF POWER-SUPPLY WIRING IN INTEGRATED CIRCUIT
Document Type and Number:
Japanese Patent JP3052519
Kind Code:
B2
Abstract:
PURPOSE: To facilitate a power supply network and the computation of currents, and to design a chip efficiently by controlling current values flowing through wirings in the laying of power-supply wirings at a desired region of the chip by wiring layers including a third or upper layer.
CONSTITUTION: A power-supply wiring is composed of first-layer grounding resistors R11-R20, first-layer power-supply wiring resistors R21-R30, second-layer grounding resistors R31-R33, second-layer power-supply wiring resistors R34-R36 and the opening-section resistors R41-R46 of a first layer and a second layer. The current values of each wiring are checked from the viewpoint of electromigration. When line width is insufficient from the same viewpoint in first layer and second layer wirings particularly among them, the width of third and fourth layer wirings is adjusted and the positions of openings of a third layer and the second layer and the positions of openings of the third and fourth layer wirings are adjusted. Current distribution is changed by the addition of the wirings of the third and fourth layer wirings, and the current values are controlled so as to reach a specified current value or less by predetermined first and second layer wiring width.
More Like This:
| JPH022652 | SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE |
| JPH04277652 | INTEGRATED CIRCUIT |
| JPH0936239 | WIRING CUTTING METHOD |
Inventors:
Soichi Ito
Application Number:
JP434192A
Publication Date:
June 12, 2000
Filing Date:
January 14, 1992
Export Citation:
Assignee:
NEC
International Classes:
H01L21/82; G06F17/50; H01L23/528; (IPC1-7): H01L21/82; G06F17/50
Domestic Patent References:
| JP63152144A | ||||
| JP2188943A | ||||
| JP6464337A |
Attorney, Agent or Firm:
Naoki Kyomoto (2 outside)