Title:
人工知能および強化学習によるシステムオンチップ（ＳｏＣ）回路の設計システムおよび方法
Document Type and Number:
Japanese Patent JP6902112
Kind Code:
B2
Abstract:
The embodiments herein discloses a system and method for designing SoC by synchronizing a hierarchy of SMDPs. Reinforcement Learning is done either hierarchically in several steps or in a single-step comprising environment, tasks, agents and experiments, to have access to SoC (System on a Chip) related information. The AI agent is configured to learn from the interaction and plan the implementation of a SoC circuit design. Q values generated for each domain and sub domain are stored in a hierarchical SMDP structure in a form of SMDP Q table in a big data database. An optimal chip architecture corresponding to a maximum Q value of a top level in the SMDP Q table is acquired and stored in a database for learning and inference. Desired SoC configuration is optimized and generated based on the optimal chip architecture and the generated chip specific graph library.
Inventors:
Najendra Nagaraja
Application Number:
JP2019558330A
Publication Date:
July 14, 2021
Filing Date:
September 25, 2017
Export Citation:
Assignee:
ALPHAICS CORPORATION
International Classes:
G06F30/33; G06F30/27; G06F30/337
Domestic Patent References:
| JP2004288205A |
Foreign References:
| US20160179162 | ||||
| US20140298281 |
Attorney, Agent or Firm:
Kenji Sugimura
Mitsutsugu Sugimura
Keita Tsuji
Mitsutsugu Sugimura
Keita Tsuji