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Title:
DETECTION CIRCUIT DEVICE AND SIGNAL DETECTION CIRCUIT SYSTEM USING THE SAME
Document Type and Number:
Japanese Patent JP2005191840
Kind Code:
A
Abstract:

To provide a detection circuit device for extracting information related with an orthogonal signal level in simple configuration and a signal detection circuit system using the device without increasing the circuit scale.

This detection circuit device is provided with a multiplier circuit 35 having a multiplier 30 to which a first non-inversion input terminal 31A, a first inversion input terminal 31B, a second non-inversion input terminal 32A and a second inversion input terminal 32B are connected. An I signal input terminal 18 is connected to the first inversion input terminal 31A and the second non-inversion input terminal 32A, and a Q signal input terminal 19 is connected to the first inversion input terminal 31B and the second inversion input terminal 32B. Either the non-inversion signal or inversion signal of a differential signal representing I components of the orthogonal signal is inputted to the I signal input terminal 18, and either the non-inversion signal or inversion signal of the differential signal representing Q components of the orthogonal signal as a second signal is inputted to a Q signal input terminal 19, so that a signal including AC components representing the level of the orthogonal signal is outputted form the multiplier 30.


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JPS59211866DETECTOR FOR PEAK
Inventors:
HASEGAWA TAKAO
KAWAMURA HIROSHI
Application Number:
JP2003429656A
Publication Date:
July 14, 2005
Filing Date:
December 25, 2003
Export Citation:
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Assignee:
SHARP KK
International Classes:
H03D1/18; H03D9/00; H04L27/18; H04L27/34; (IPC1-7): H03D1/18; H03D9/00; H04L27/18; H04L27/34
Attorney, Agent or Firm:
Hiroshi Yamazaki
Atsushi Maeda
Yukinori Nakakura