Title:
検知装置、半導体装置
Document Type and Number:
Japanese Patent JP7350768
Kind Code:
B2
Abstract:
The power of a semiconductor device is reduced. The semiconductor device includes a latch circuit composed of a dynamic circuit. The latch circuit includes a first circuit having a decoding function, a plurality of capacitors, a plurality of clock input terminals, a signal input terminal, a first output terminal, and a second output terminal. In a period during which “H” is supplied to a first clock signal, the potential of the first capacitor is updated on the basis of the results of decoding performed by the first circuit. In a period during which “H” is supplied to a second clock signal, the potential of the second capacitor is updated on the basis of the potential of the first capacitor, and the potential of the second capacitor is supplied as a first output signal to the first output terminal. In a period during which “H” is supplied to a third clock signal, the potential of the third capacitor is updated on the basis of the potential of the second capacitor, and the potential of the third capacitor is supplied as a second output signal to the second output terminal.
Inventors:
Shintaro Harada
Takayuki Ikeda
Takayuki Ikeda
Application Number:
JP2020552182A
Publication Date:
September 26, 2023
Filing Date:
October 17, 2019
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
G11C11/401; H03K3/356; H03K23/00; H03K23/44
Domestic Patent References:
| JP6010498A | ||||
| JP2000349163A | ||||
| JP51112142A | ||||
| JP2016105590A | ||||
| JP7177000A |
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