To detect a signal rate that is used at a multiplex data rate by having a 1st receiver part operated when a 1st comparator detects a comparatively low data rate signal and having a 2nd receiver part operated when a 2nd comparator detects a comparatively high data rate signal respectively.
A parallel detection circuit 403 has two comparators CMP 10 (404) and CMP 100 (405). The CMP 10 sets a flip-flop FF 10 by its own output and sends the output of the FF 10 to an FLP block 408 and an NLP block 409 in a polling cycle. When the NLP signal sent from the block 409 or the 10 BT signal sent from a block 407 is active, an OR gate 411 sets a 10 BT receiver 401 in its operable state. Meanwhile, an OR gate 412 sets a 100 TX receiver 402 in its operable state when the SD signal sent from a block 410 or the 100 TX signal sent from the block 407 is active.
AYAL SHOVAL
MATTHEW TOTA
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