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Title:
DETERMINING SYSTEM FOR INTERRUPT PRIORITY LEVEL
Document Type and Number:
Japanese Patent JPS582952
Kind Code:
A
Abstract:

PURPOSE: To improve a processing speed practically, by controlling the allowable queuing time by a hardware in the real-time processing system using a microprocessor.

CONSTITUTION: When interrupt inputs (a)W(c) come, corresponding counter parts 5W7 are preset to respective allowable queuing times in accordance with these interrupts. Then, an interrupt generating part 8 transmits information to a central processing part so that the central processing part executes the processing for the interrupt which corresponds to one of counters 5W7 to which the shortest queuing time is set. After the processing is terminated, this corresponding counter is reset and is not operated until the next interrupt. Consequently, when plural interruption causes exist, the interruption processing is executed effectively in respect to time.


Inventors:
TANIGUCHI YOSHIHIKO
OOTA KOUICHI
SUZUKI HAYASHI
Application Number:
JP10109881A
Publication Date:
January 08, 1983
Filing Date:
June 29, 1981
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G06F9/48; (IPC1-7): G06F9/46
Attorney, Agent or Firm:
Koshiro Matsuoka



 
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